Designing from VHDL Behavioral Description to FPGA Implementation

ion level Simulation time VHDL code sizeBehavioral3 sec.84High RTL6 sec.236Synthesizable RTL8 sec.321Gate level170 sec.727Test bench le|136Table 1: The comparison of VHDL descriptions of the design on the di erent ab-straction levels.Synthesis[min] 12Area [gates]216Max. Delay [ns] 48,3Table 2: Some characteristics of synthesis of CRC module.was mapped onto an XC4002 Xilinx FPGA. Each design phase was supported bytools. The translation of les to di erent le formats demanded by particular toolsshowed the number of interfacing bugs which have to be resolved. To overcome thisdi culties, we developed a number of programs for le translations.The translation from behavioral into RTL description was not supported by anycommercial tool. The proper high level synthesis tool would help, as this step is themost time consuming step in the complete designing process.AcknowledgmentThe authors would like to thank Michael K. Gschwind for his support and helpfuldiscussions.References[80283]ANSI/IEEE Std 802.3. IEEE standars for local area networks: Car-rier sense multiple access with collision detection (CSMA/CD) accessmethod and physical layer speci cations. IEEE, Inc, June 1983.[BE93]Matthias Bauer and Wolfgang Ecker. Communication mechanisms forVHDL speci cation and designstarting at system level. InVHDL Forumfor CAD in Europe, pages 95{105, March 1993.[Gei93]Olaf Geisler. VHDL based synthesis of a high speed full parallel 32 bitCRC generator/checker. In VHDL Forum for CAD in Europe, pages133{137, March 1993.6 [HAWW89] F. Hady, J. Aylor, R. Williams, and R. Waxman. Uninterpreted mod-eling using the VHSIC Hardware Description Language (VHDL). InInternational Conference on Computer Aided Design, pages 172{175,1989.[IEE88] IEEE, Inc. IEEE Standard VHDL Language Reference Manual, March1988.[Nat90]National Semiconductor Corporation. DP83932 System Oriented Net-work Interface Controller, May 1990.[Pre94]Viktor Preis. An approach to complex and self-generating VHDL mod-els for simulation and synthesis. In VHDL Forum for CAD in Europe,pages 39{45, April 1994.[Sal92]Valentina Salpura. VHDL model of DP83932 system oriented networkinterface controller. Technical report, TU Wien, 1992.[SMG93] Manfred Selz and Klaus-Dieter Muller-Glase. Synthesis with VHDL.In VHDL Forum for CAD in Europe, pages 31{40, March 1993.[SYN92a] SYNOPSYS, Inc. Design Compiler Reference Manual Version 3.0, De-cember 1992.[SYN92b] SYNOPSYS, Inc. System Simulator Reference Manual Version 3.0,December 1992.[TM91]D. E. Thomas and P. R. Moorby. The Verilog Hardware DescriptionLanguage. Boston, MA, kluwer academic publishers edition, 1991.[Xil93]Xilinx, Inc., San Jose. The Programmable Gate Array Data Book, 1993.7